The present invention relates to a semiconductor device, a manufacturing method thereof, and a monolithic microwave integrated circuit, and more specifically to a semiconductor device and a manufacturing method thereof suitable for MMIC (monolithic microwave integrated circuit) and the like for microwave and millimeterwave band applications.
In view of improving gain and stability of MMIC (monolithic microwave integrated circuit), a via hole technology is essential for compound semiconductor MMIC because via holes may decrease ground inductances.
For example, a technology for forming a via hole from the surface of a semiconductor has been disclosed in Japanese Patent Laid-Open Publication No. HEI 7-135210. Detailed description will be given of the case where this prior art technology is applied to a GaAs HBT (hetero-junction bipolar transistor) MMIC for microwave band application shown in FIG. 28 as an example.
FIG. 28 is a plane view showing a structure of the prior art technology applied to an amplifier GaAs HBT-MMIC for microwave band application composed of a semiconductor device.
As shown in FIG. 28, the amplifier GaAs MMIC for microwave band application is composed of a first HBT element 101a, a second HBT element 101b, a third HBT element 101c, an MIM (metal-insulator-metal) capacitor 102, a spiral inductor 103, a resistive element 104, an input pad electrode 105, an output pad electrode 106, pad electrodes for HBT element control 107a and 107b, and a ground electrode 108.
A via hole manufacturing method by the prior art technology is applicable to the ground electrode 108 in the vicinity of the first HBT element 101a. 
FIGS. 29 to 32 show conventional process for manufacturing semiconductor devices in sequence as disclosed in the above document.
In this manufacturing process, first as shown in a cross sectional view of FIG. 29, there are formed a ground electrode 108 and an emitter electrode 111, and then a first resist film 112 having an airbridge interconnection pattern is formed. Next, a first feeding layer 113 is formed on the entire surface.
Next as shown in a cross sectional view of FIG. 30, there is formed a second resist film 114 having a via hole pattern. Then as shown in a cross sectional view of FIG. 31, the first feeding layer 113 and a substrate 115 are etched down with the second resist film 114 used as a mask to form a via hole 116.
Next as shown in a cross sectional view of FIG. 32, a second feeding layer 117 is formed, and then electrolytic plating is executed with use of a third resist mask 118 having a specified pattern to integrate an airbridge interconnection 119 and an interconnection inside the via hole 116.
Next as shown in a cross sectional view of FIG. 33, with the substrate 115 being attached to a support substrate (unshown), the back surface of the substrate 115 is etched away till a plated metal inside the via hole 116 is exposed. Further, a backside electrode 120 is formed on the entire surface to complete a compound semiconductor MMIC as shown in FIG. 28.
However, in the prior art technology, only a single via hole 116 is formed in each ground electrode 108 connected by the airbridge interconnection 119. Accordingly, reducing a ground inductance without changing an aperture area of the via hole 116 requires plating of a thicker metal film inside the via hole 116.
However, in the prior art technology, the airbridge interconnection 119 is plated and formed together with the metal film inside the via hole 116, which makes the thickness of a plated metal film forming the airbridge interconnection 119 larger. As a result, the third resist mask 118 is also required to be a thick negative resist.
However, usage of a thick negative resist for the third resist mask 118 causes such problems as deterioration of alignment precision and difficulty in obtaining apertures of fine line patterns.
Therefore, usage of a thick negative resist is not suited for the interconnection patterns that require alignment precision and fine lines like airbridge interconnections. This makes it impossible to increase the thickness of the plated metal inside the via hole 116, which gives the prior art technology a limit of reducing the ground inductance of the via hole.
Here, forming the airbridge interconnection 119 prior to forming the via hole 116 may be considered as a candidate solution.
However, reducing the ground inductance of one via hole 116 requires increase in thickness of a plated metal film, which causes large difference in thickness between a plated metal film forming the airbridge interconnection and a plated metal film in the vicinity of the via hole 116. As a result, unevenness on the front surface of the substrate 115 becomes larger, and therefore in etching the back surface of the substrate 115 while the front surface being attached to the support substrate, external force is concentrated at a part of the semiconductor substrate 115. As a consequence, there are caused problems that semiconductor substrates are broken or inclined, thereby affecting precision of the substrate thickness.
In addition, when an aperture area of the via hole is increased for reducing the ground inductance, an area of an MMIC chip is also increased, which prevents downsizing.